core/stdarch/crates/core_arch/src/loongarch_shared/
mod.rs

1//! `Shared LoongArch` intrinsics
2
3use crate::arch::asm;
4
5/// Reads the lower 32-bit stable counter value and the counter ID
6#[inline]
7#[unstable(feature = "stdarch_loongarch", issue = "117427")]
8pub fn rdtimel_w() -> (i32, isize) {
9    let (val, tid): (i32, isize);
10    unsafe { asm!("rdtimel.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)) };
11    (val, tid)
12}
13
14/// Reads the upper 32-bit stable counter value and the counter ID
15#[inline]
16#[unstable(feature = "stdarch_loongarch", issue = "117427")]
17pub fn rdtimeh_w() -> (i32, isize) {
18    let (val, tid): (i32, isize);
19    unsafe { asm!("rdtimeh.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)) };
20    (val, tid)
21}
22
23#[allow(improper_ctypes)]
24unsafe extern "unadjusted" {
25    #[link_name = "llvm.loongarch.crc.w.b.w"]
26    fn __crc_w_b_w(a: i32, b: i32) -> i32;
27    #[link_name = "llvm.loongarch.crc.w.h.w"]
28    fn __crc_w_h_w(a: i32, b: i32) -> i32;
29    #[link_name = "llvm.loongarch.crc.w.w.w"]
30    fn __crc_w_w_w(a: i32, b: i32) -> i32;
31    #[link_name = "llvm.loongarch.crcc.w.b.w"]
32    fn __crcc_w_b_w(a: i32, b: i32) -> i32;
33    #[link_name = "llvm.loongarch.crcc.w.h.w"]
34    fn __crcc_w_h_w(a: i32, b: i32) -> i32;
35    #[link_name = "llvm.loongarch.crcc.w.w.w"]
36    fn __crcc_w_w_w(a: i32, b: i32) -> i32;
37    #[link_name = "llvm.loongarch.dbar"]
38    fn __dbar(a: i32);
39    #[link_name = "llvm.loongarch.ibar"]
40    fn __ibar(a: i32);
41    #[link_name = "llvm.loongarch.movgr2fcsr"]
42    fn __movgr2fcsr(a: i32, b: i32);
43    #[link_name = "llvm.loongarch.movfcsr2gr"]
44    fn __movfcsr2gr(a: i32) -> i32;
45    #[link_name = "llvm.loongarch.iocsrrd.b"]
46    fn __iocsrrd_b(a: i32) -> i32;
47    #[link_name = "llvm.loongarch.iocsrrd.h"]
48    fn __iocsrrd_h(a: i32) -> i32;
49    #[link_name = "llvm.loongarch.iocsrrd.w"]
50    fn __iocsrrd_w(a: i32) -> i32;
51    #[link_name = "llvm.loongarch.iocsrwr.b"]
52    fn __iocsrwr_b(a: i32, b: i32);
53    #[link_name = "llvm.loongarch.iocsrwr.h"]
54    fn __iocsrwr_h(a: i32, b: i32);
55    #[link_name = "llvm.loongarch.iocsrwr.w"]
56    fn __iocsrwr_w(a: i32, b: i32);
57    #[link_name = "llvm.loongarch.break"]
58    fn __break(a: i32);
59    #[link_name = "llvm.loongarch.cpucfg"]
60    fn __cpucfg(a: i32) -> i32;
61    #[link_name = "llvm.loongarch.syscall"]
62    fn __syscall(a: i32);
63    #[link_name = "llvm.loongarch.frecipe.s"]
64    fn __frecipe_s(a: f32) -> f32;
65    #[link_name = "llvm.loongarch.frecipe.d"]
66    fn __frecipe_d(a: f64) -> f64;
67    #[link_name = "llvm.loongarch.frsqrte.s"]
68    fn __frsqrte_s(a: f32) -> f32;
69    #[link_name = "llvm.loongarch.frsqrte.d"]
70    fn __frsqrte_d(a: f64) -> f64;
71}
72
73/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
74#[inline]
75#[unstable(feature = "stdarch_loongarch", issue = "117427")]
76pub fn crc_w_b_w(a: i32, b: i32) -> i32 {
77    unsafe { __crc_w_b_w(a, b) }
78}
79
80/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
81#[inline]
82#[unstable(feature = "stdarch_loongarch", issue = "117427")]
83pub fn crc_w_h_w(a: i32, b: i32) -> i32 {
84    unsafe { __crc_w_h_w(a, b) }
85}
86
87/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
88#[inline]
89#[unstable(feature = "stdarch_loongarch", issue = "117427")]
90pub fn crc_w_w_w(a: i32, b: i32) -> i32 {
91    unsafe { __crc_w_w_w(a, b) }
92}
93
94/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
95#[inline]
96#[unstable(feature = "stdarch_loongarch", issue = "117427")]
97pub fn crcc_w_b_w(a: i32, b: i32) -> i32 {
98    unsafe { __crcc_w_b_w(a, b) }
99}
100
101/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
102#[inline]
103#[unstable(feature = "stdarch_loongarch", issue = "117427")]
104pub fn crcc_w_h_w(a: i32, b: i32) -> i32 {
105    unsafe { __crcc_w_h_w(a, b) }
106}
107
108/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
109#[inline]
110#[unstable(feature = "stdarch_loongarch", issue = "117427")]
111pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
112    unsafe { __crcc_w_w_w(a, b) }
113}
114
115/// Generates the memory barrier instruction
116#[inline]
117#[unstable(feature = "stdarch_loongarch", issue = "117427")]
118pub fn dbar<const IMM15: i32>() {
119    static_assert_uimm_bits!(IMM15, 15);
120    unsafe { __dbar(IMM15) };
121}
122
123/// Generates the instruction-fetch barrier instruction
124#[inline]
125#[unstable(feature = "stdarch_loongarch", issue = "117427")]
126pub fn ibar<const IMM15: i32>() {
127    static_assert_uimm_bits!(IMM15, 15);
128    unsafe { __ibar(IMM15) };
129}
130
131/// Moves data from a GPR to the FCSR
132#[inline]
133#[unstable(feature = "stdarch_loongarch", issue = "117427")]
134pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
135    static_assert_uimm_bits!(IMM5, 5);
136    __movgr2fcsr(IMM5, a);
137}
138
139/// Moves data from a FCSR to the GPR
140#[inline]
141#[unstable(feature = "stdarch_loongarch", issue = "117427")]
142pub fn movfcsr2gr<const IMM5: i32>() -> i32 {
143    static_assert_uimm_bits!(IMM5, 5);
144    unsafe { __movfcsr2gr(IMM5) }
145}
146
147/// Reads the 8-bit IO-CSR
148#[inline]
149#[unstable(feature = "stdarch_loongarch", issue = "117427")]
150pub unsafe fn iocsrrd_b(a: i32) -> i32 {
151    __iocsrrd_b(a)
152}
153
154/// Reads the 16-bit IO-CSR
155#[inline]
156#[unstable(feature = "stdarch_loongarch", issue = "117427")]
157pub unsafe fn iocsrrd_h(a: i32) -> i32 {
158    __iocsrrd_h(a)
159}
160
161/// Reads the 32-bit IO-CSR
162#[inline]
163#[unstable(feature = "stdarch_loongarch", issue = "117427")]
164pub unsafe fn iocsrrd_w(a: i32) -> i32 {
165    __iocsrrd_w(a)
166}
167
168/// Writes the 8-bit IO-CSR
169#[inline]
170#[unstable(feature = "stdarch_loongarch", issue = "117427")]
171pub unsafe fn iocsrwr_b(a: i32, b: i32) {
172    __iocsrwr_b(a, b)
173}
174
175/// Writes the 16-bit IO-CSR
176#[inline]
177#[unstable(feature = "stdarch_loongarch", issue = "117427")]
178pub unsafe fn iocsrwr_h(a: i32, b: i32) {
179    __iocsrwr_h(a, b)
180}
181
182/// Writes the 32-bit IO-CSR
183#[inline]
184#[unstable(feature = "stdarch_loongarch", issue = "117427")]
185pub unsafe fn iocsrwr_w(a: i32, b: i32) {
186    __iocsrwr_w(a, b)
187}
188
189/// Generates the breakpoint instruction
190#[inline]
191#[unstable(feature = "stdarch_loongarch", issue = "117427")]
192pub unsafe fn brk<const IMM15: i32>() {
193    static_assert_uimm_bits!(IMM15, 15);
194    __break(IMM15);
195}
196
197/// Reads the CPU configuration register
198#[inline]
199#[unstable(feature = "stdarch_loongarch", issue = "117427")]
200pub fn cpucfg(a: i32) -> i32 {
201    unsafe { __cpucfg(a) }
202}
203
204/// Generates the syscall instruction
205#[inline]
206#[unstable(feature = "stdarch_loongarch", issue = "117427")]
207pub unsafe fn syscall<const IMM15: i32>() {
208    static_assert_uimm_bits!(IMM15, 15);
209    __syscall(IMM15);
210}
211
212/// Calculate the approximate single-precision result of 1.0 divided
213#[inline]
214#[target_feature(enable = "frecipe")]
215#[unstable(feature = "stdarch_loongarch", issue = "117427")]
216pub fn frecipe_s(a: f32) -> f32 {
217    unsafe { __frecipe_s(a) }
218}
219
220/// Calculate the approximate double-precision result of 1.0 divided
221#[inline]
222#[target_feature(enable = "frecipe")]
223#[unstable(feature = "stdarch_loongarch", issue = "117427")]
224pub fn frecipe_d(a: f64) -> f64 {
225    unsafe { __frecipe_d(a) }
226}
227
228/// Calculate the approximate single-precision result of dividing 1.0 by the square root
229#[inline]
230#[target_feature(enable = "frecipe")]
231#[unstable(feature = "stdarch_loongarch", issue = "117427")]
232pub fn frsqrte_s(a: f32) -> f32 {
233    unsafe { __frsqrte_s(a) }
234}
235
236/// Calculate the approximate double-precision result of dividing 1.0 by the square root
237#[inline]
238#[target_feature(enable = "frecipe")]
239#[unstable(feature = "stdarch_loongarch", issue = "117427")]
240pub fn frsqrte_d(a: f64) -> f64 {
241    unsafe { __frsqrte_d(a) }
242}